caching - Cache miss penalty in deep RISC pipeline -

why cache miss penalty greater in pipelined processor?

is because stalling period more if miss occurs @ late stage of pipeline? or because there many instructions in pipeline?

usually implement deeper pipeline reduce cycle time of each pipe stage.

consider 2 in-order single-issue pipelined processor microarchitectures.

ua1 has 5 stage pipeline , 2 ns cycle time. ua2 has 10 stage pipeline , 1 ns cycle time.

a full cache miss must (at least) load entire cache line dram. assume takes 100 ns, including row activation, burst reads of line words, , row precharge.

when ua1 takes cache miss, stalls 100 ns, e.g. 50 clock cycles, e.g. 50 issue slots. when ua2 takes cache miss, stalls 100 ns, e.g. 100 clock cycles, e.g. 100 issue slots.

here cache miss penalty (expressed in instruction issue slots missed), twice large in more pipelined processor.