fsm - Encoding state machines in VHDL -
i'm looking creating system in vhdl filters image after receiving through ftdi usb-to-serial device. part of this, believe i've identified states cpld should in, have never created complex state machine in vhdl before, i'm questioning whether methods sound. currently, basic outline state machine thus:
begin process(clk, reset, usb_rxfn, usb_txen) begin case state when idle => when negotiating => when receiving => when filtering => when transmitting => when others => -- should never happen go idle end process;
my problem here every state machine tutorial i've been able find changes state on every rising edge (or similar, once per clock) , device should sit in idle lot , transition negotiating when usb_rxfn goes low, stay in negotiating until that's done, stay in receiving until entire image has been transferred etc...
is there fundamentally flawed in approach? cpld's unsuited purpose? or possible stay in state more single clock , tutorials written way simplicity?
in brief, tutorials you've read have been written way simplicity.
it's ok wait event in state before moving another. can expressed in many ways in vhdl, 1 common way have both state
, nextstate
signals, like:
architecture foo of bar type statetype (idle, negotiating, receiving, filtering, transmitting); signal state : statetype; signal nextstate : statetype; begin fsm: process(clk, reset) begin if reset='1' state <= idle; elsif clk'event , clk='1' state <= nextstate; end if; end process fsm; states: process(state, usb_rxfn, usb_txen) -- ... begin nextstate <= state; -- default, stay in same state (avoid latch while you're @ it) case state when idle => if usb_rxfn='0' nextstate <= negotiating; end if; -- etc end case; end process states; end foo;
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